Direct-current to direct current (DC/DC) converters are widely used in the field of electronics. Such circuitry or devices, which are typically employed to convert an input DC voltage into a predetermined stable DC voltage by switching-control of a semi-conductor device, are well known, and constitute a vital part in power supplies in various electronic apparatuses. For fast microprocessors and chipsets, a DC/DC controller needs to have fast responses in order to meet the load transient response requirements of the microprocessors and chipsets. However, the fast reaction might cause stability issues of the DC/DC converter for the electrical circuit. Conventional voltage mode and current mode controllers are very stable due to their external compensation networks, but fail to meet the load transient response specifications. In order to ensure stability and mitigate the load transient behavior, the switching frequency is pushed to higher frequencies and the ESR (Equivalent Series Resistance) of filtering capacitors should be high enough in order to assure enough phase margin. The stability of a DC/DC converter is essentially based on the ESR of the output decoupling capacitors. However, typical output ceramic decoupling capacitors cannot be used because of their low ESR, which will be described in details hereinafter.
Referring to PRIOR ART FIG. 1, a typical prior art DC/DC converter 100 is illustrated. The DC/DC converter 100 is used to convert an input voltage (Vin) to a predetermined output voltage on a load 120, and comprises two switches 102 and 104, an inductor 106, a capacitor 108, resistors 112 and 114, and a controller 116. The switch 102 is coupled to the input voltage of the DC/DC converter 100 and to the inductor 106. The switch 104 couples the switch 102 and the inductor 106 to ground. The switches 102 and 104 serve as a switching circuit for receiving and converting the input voltage to a predetermined output voltage.
The controller 116 is coupled to the switch 102 at a HDR pin and the switch 104 at a LDR pin to control the conductive states of switches 102 and 104 and further to control the output voltage of the DC/DC converter 100. It will be apparent to those skilled in the art that PWM signals will be delivered from the HDR pin and the LDR pin of the controller 116 so as to regulate the output voltage of the DC/DC converter 100 to the predetermined output voltage.
The two ends of the inductor 106 are coupled to the switch 102 and an output node of the DC/DC converter 100, respectively. The capacitor 108 is coupled to the output node of the DC/DC converter 100. The inductor 106 and the capacitor 108 form a low pass filter to smooth the output of the DC/DC converter 100. It will be apparent to those skilled in the art that the resistor 110 is an inherent parasitic resistance or an Equivalent Series Resistance (ESR) of the capacitor 108.
The resistors 112 and 114 serve as a voltage divider. The resistors 112 and 114 are coupled to each other in series for coupling the output node of the DC/DC converter 100 to ground so as to generate a divided voltage of the output voltage at the common node of the resistors 112 and 114. The divided voltage serves as a feedback signal of the output voltage, and is coupled to the voltage feedback pin (VFB) of the controller 116. The controller 116 controls the switch 102 and the switch 104 in response to the feedback signal at node VFB so as to precisely deliver the predetermined output voltage.
It will be apparent to those skilled in the art that the voltage ripple on the capacitor 108 is proportional to the current ripple of the inductor 106. The voltage on the capacitor 108 is divided by the resistors 112 and 114. The zero frequency or the frequency of the zero, Fz, introduced by the capacitor 108 can be calculated in Equation (1) as follows:
                    Fz        =                  1`                      2            ⁢                                                  ⁢            π            *            Cout            *            ESR                                              (        1        )            Where Cout is the capacitance of capacitor 108 and ESR is the ESR value of the capacitor 108 or the resistance value of the resistor 110.
The stability condition in this case is to assure the zero frequency Fz introduced by the capacitor 108 combined with the ESR resistor 110 to be low enough so as to partially reduce or compensate the influence of the LC double pole, e.g. the inductor 106 and the capacitor 108. From the equation (1), it is understood that the resistor 110, i.e., the ESR of the capacitor 108, has to be high enough to ensure a low zero frequency Fz. However, the ESR value of a ceramic decoupling capacitor is relatively small. Thus, an inexpensive output ceramic decoupling capacitor may not be employed in the DC/DC converter 100.
Ceramic capacitors have high capacitance and low ESR, and are inexpensive. It is desirable to use ceramic capacitors. DC/DC converters that are unfit to use ceramic output capacitors for stability reasons may be bulkier and more expensive. Another disadvantage of the topology shown in PRIOR ART FIG. 1 is that the output voltage ripple has to be high enough in order to assure stability since the output voltage ripple at the voltage feedback node VFB of the controller 120 is divided by the voltage divider. The voltage ripple at the feedback node VFB in turn assures stable PWM operation. This problem encountered in the prior art will be explained hereinafter in detail.